The present invention is used for high speed data transmission, and especially for optical fiber data transmission systems that multiplex and distribute high speed data.
Here, the prior art of channel selection method described in Japanese Patent Laid-Open No.42929 (1991) is explained.
FIG. 10 is a block diagram showing the channel selection method described in the above-mentioned Published Unexamined Patent Application.
In this figure, 101 is a transmitter.
102 to 105 are data transmission circuits for receiving data from data input terminals D1 to D4 respectively and outputting the data at respective timing.
106 is a bit multiplexing circuit for time division multiplexing data output from the data transmission circuits 102 to 105 and outputting a serial transmission data to a reception side.
107 is a first frequency divider for frequency dividing a transmission clock into 1/4 and supplying pulses of which timing are different each other to the data transmission circuits 102 to 105.
108 is a clock generation circuit for supplying the transmission clock to the bit multiplexing circuit 106, the frequency divider 107 and the reception side.
109 is a channel information addition circuit for detecting channel information input from a channel information input terminal CH1 and supplying this channel information to the bit multiplexing circuit 106, the frequency divider 107 and the clock generation circuit 108. The channel information consists of channel numbers and information on number of all channels.
110 is a receiver.
111 is a data reception circuit for selecting channels in the serial transmission data and extracting data of a specified channel.
112 is a clock reception circuit for receiving the transmission clock.
113 is a gate circuit for opening and closing at every one clock based on the channel information and channel selection information input into a channel selection input terminal CHS and controlling the transmission clock.
114 is a second frequency divider for frequency dividing the clock from the gate circuit 113 into 1/4.
115 is a channel information detection circuit for detecting channel information from among reception data.
OUT is an output terminal of reception data.
Next, operation of the above-mentioned channel selection method is explained.
First, the clock generation circuit 108 generates a clock signal at transmission speed of the system trunk line within the transmitter 101.
The frequency divider 107 frequency divides the clock signal into 1/4 and supplies the divided clock signals to the data transmission circuits 102 to 105.
The data transmission circuits 102 to 105 output bit data at different timing in parallel.
The bit multiplexing circuit 106 time division multiplexes outputs from the data transmission circuits 102 to 105 to make them a serial data.
On the other hand, the channel information addition circuit 109 receives channel information from the channel information input terminal CH1 and gives channel information to the bit multiplexing circuit 106 via the clock generation circuit 108 and the frequency divider 107.
Then, the bit multiplexing circuit 106 adds channel information on the above-mentioned serial data to make a serial transmission data and transmits the serial transmission data to the receiver 110 in synchronizing with the transmission clock.
The data reception circuit 111 in the receiver 110 extracts and receives data of the specified channel from among the serial transmission data transmitted in synchronizing with the above-mentioned transmission clock.
The synchronization signal used for this extraction operation is the transmission clock, which has been received in the clock reception circuit 112, divided into 1/4 in the frequency divider 114 as shown in FIG. 11.
Where, in FIG. 11, A is transmission side, B is reception side, a is a serial transmission data in which parallel data of channels 1 to 4 are multiplexed, b is a transmission clock and c is a transmission clock that is frequency divided into 1/4.
Next, channel switching operation is explained.
FIG. 12 and FIG. 13 are figures to explain channel switching operation.
Where, in these figures, a is a transmission clock, b is a frequency division output output from the frequency divider 114 and c is a serial transmission data.
First of all, for carrying out channel switching, currently receiving channel number and number of all channels are recognized by detecting channel information from a current channel in the channel information detection circuit 115.
Here, the case of switching channel from channel 1 to channel 4 is considered as shown in FIG. 12.
In this case, the gate circuit 113 firstly prohibits 3 clocks (=4 clocks-1 clock) among 4 clocks of the transmission clocks and outputs the result to the frequency divider 114. Thus, channel 1 is switched to channel 4.
In FIG. 12, the three clocks, which are drawn by dotted lines on the frequency division output b, show the prohibited clocks, numbers on the serial transmission data c are data according to channel numbers and each channel number marked by a circle shows data of the channel number that is received.
FIG. 13 shows the case of switching channel from channel 3 to channel 1.
In this case, the gate circuit 113 firstly prohibits 2 clocks (=4 clocks-(3 clocks-1 clock)) among 4 clocks of the transmission clocks and outputs the result to the frequency divider 114. Thus, channel 3 is switched to channel 1.
Like this, in the prior art, the transmission side must add all channel information onto a transmission data and the reception side must extract channel information from an arbitrary channel and control channel selection.
By this reason, the prior art has a problem that the circuit becomes complicated and the receiver becomes large for signal processing. In addition, if signals of which transmission speed are not same are mixed, the signal processing becomes more complicated.